One currently favored class of random access memory employs the so-called "one-device" cell. Disclosed as early as 1968, for example, in U.S. Pat. No. 3,287,286 to Dennard, the one-device cell has found favor among memory designers because of its small cell size, high speed, and low power dissipation. Basically, the one-device cell includes a single active device (typically a bipolar or field effect transistor) and a single charge storage device (typically a capacitor). The active device's controlling electrode (i.e., the base or gate) is connected to a word line for selecting the cell. One of the active device's controlled electrodes (i.e., the bipolar transistor's emitter or collector or the field effect transistor's drain or source) is connected to one of the capacitor plates. The other capacitor plate is connected to a fixed potential, typically ground or the memory power supply voltage. Finally, the other of the active device's controlled electrodes is connected to a bit line. A sense amplifier is also connected to the bit line for sensing the binary data stored in the cell.
The binary state of the one-device cell is determined by the charge stored on the capacitor thereof. For example, the presence of charge on the capacitor may signify a logical ZERO while the absence of charge on the capacitor may signify a logical ONE. During the standby state, the controlling electrode (i.e., the base or gate) is disabled so that the active device is off, and acts as a high impedance to prevent capacitor discharge. Data is read (sensed) by turning on the active device, which permits the capacitor to discharge onto the bit line to which the active device is connected. This charge is sensed by the sense amplifier connected to the bit line.
Many of the desirable memory characteristics discussed above are inherent in a memory comprising one-device cells (hereinafter referred to as a "one-device memory"). For example, only two components per cell are needed, thus occupying minimal integrated circuit chip "real estate". The one-device memory is also high speed because of the rapid capacitor charge/discharge rate. Finally, no power is dissipated during the standby state.
Recently, an attempt has been made to extract even greater performance from the one-device memory by tying the normally grounded capacitor plate to a line which runs parallel to the bit line, and differentially sensing the read signal between the added line and the original bit line. As shown in IBM Technical Disclosure Bulletin, Vol. 23, No. 6, pp. 2331-2332 (November 1980), the one device cells are located between a pair of bit lines which are connected to the respective nodes of a differential sense latch. This causes a differential signal to be applied to the sense latch, and eliminates reference signals or dummy cells. To ensure balanced bit line capacitances, each bit line is divided into equal alternating portions of polysilicon and diffused sections, and alternate pairs of cells in a row are inverted by interchanging the location of the cell's active device and charge storage device.
By utilizing the charge stored on both plates of the capacitor, rather than dissipating the charge on one plate into ground, the above identified Technical Disclosure Bulletin increases the sense signal from the cell. However, this increased sense signal must not occur at the expense of memory reliability. For example, it must be assured that the data in an unselected cell is not disturbed during a read/write operation from a selected cell. Moreover, an arrangement must be found for maximizing the increased sense signal which is available from the differentially sensed cell. In short, there is a need for a new one-device memory arrangement which takes maximum advantage of the increased signal which may be obtained by adding a line to the normally grounded capacitor plate and differentially sensing the signal between the bit line and the added line.